The present invention relates to error performance analyzers. This application for patent is a continuation-in-part of an application filed on Nov. 28, 2000, titled xe2x80x9cMethod And Apparatus For Characterizing Frequency Response Of An Error Performance Analyzerxe2x80x9d, Ser. No. 09/723,704, now abandoned. More specifically, the present invention relates to the method and apparatus for determining frequency response of a device under test using error performance analyzers.
A fundamental measure of quality of digital circuits, switches, and transmission systems is the probability of any stored or transmitted bit being transmitted in error, or bit error ratio (BER). The BER is typically tested using a bit error ratio tester (BERT) which may include of a pattern generator and an error detector. The pattern generator and the error detector are often combined in a single unit though this is not required and are, in fact, sometimes separate units. The pattern generator generates a known sequence of bits (sequence of zeros and ones) for transmission through a device under test (DUT). Typically, the known sequence of bits is often generated by a pseudo-random bit sequencer (PRBS) and is of known length of 2Nxe2x88x921 bits where N may be any number. For example, typical values for N are seven (7) or ten (10). For convenience, the known sequence of bits is referred to as a base bit sequence, or a base bit pattern. The base bit pattern is continually repeated by the pattern generator.
The repeated base bit pattern is transmitted to the BUT which, in turn, transmits the bit sequences to be received by the error detector. The error detector compares the received bit sequence with the known bit sequence for error bit detection. Usually, the error detector also generates the known sequence of bits, or repeated base bit pattern, such that the error detector can compare the received bit sequence with the known bit sequence to detect errors in transmission. An error bit is a bit that is sent to the DUT as a zero but transmitted by the DUT as a one, or a bit that is sent to the DUT as a one but transmitted by the DUT as a zero. Then, the number of error bits is compared with the number of bits received. The ratio of the error bits to the sent bits is the bit error ratio, BER. With modern devices, the BER tends to be very low and can be on the order of 10-12 or even less.
As discussed, an error detector provides the BER as one measure of quality of the DUT. However, to determine frequency response of the DUT, a network analyzer is typically used. A network analyzer creates a data model of the transfer characteristic of a linear network over the frequency range of interest. The uses of the network analyzer and the technique of obtaining frequency response of a DUT using the network analyzer are known in the art.
In summary, to test a DUT for its error rate as well as for frequency response, two devices are neededxe2x80x94a BERT and a network analyzer. However, the use of the network analyzer adds to the hardware requirements and costs to the DUT testing process. It would be preferable to analyze the frequency response of the DUT using the BERT alone. Accordingly, there is a need for a technique and an apparatus to obtain the BER as well as to obtain frequency response without the use of a network analyzer.
These needs are met by the present invention. According to one embodiment of the present invention, a technique of characterizing the frequency response of a device under test (DUT) using an error performance analyzer is disclosed. First, a bit sequence comprising repeated base bit pattern, the base bit pattern having a first transition from a first bit voltage, VLB, to a second bit voltage, VHB is received. Then, using bit error rate distribution, multivalue voltages along the first transition is determined. Finally, the transition voltages are converted into frequency domain to characterize frequency response of the DUT.
According to another embodiment of the present invention, an apparatus including a processor and storage connected to the processor. The storage includes instructions for the processor to receive a bit sequence comprising repeated base bit pattern, the base bit pattern having a first transition from a first bit voltage, VLB, to a second bit voltage, VHB. Further, the storage includes instructions for the processor to determine, using bit error rate distribution, multivalue voltages for a predetermined period of time from an initial sample time, TS0, to a final sample time, TSM. Finally, the storage includes instructions for the processor to convert the multivalue voltages into frequency domain to characterize frequency response of the DUT.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example, the principles of the present invention.